Numerical convergence in
Spice simulators is closely coupled to the concept of the error
in numerical integration. Reducing the time step reduces numerical
integration errors. The error boundary for the numerical integration
is estimated and is the basis for setting the transient step
time. For many circuits, simulations contain sharp voltage steps
that are not constrained by numerical integration. When this
occurs, integration accuracy is unaffected so that the simulator
is allowed a large time step. This results in a loss in accuracy
because the excessively large time steps can jump over needed
details. In the past, it was necessary to restrict this behavior
by setting Tmax in the .TRAN statement. The January 2000 newsletter
(http://www.intusoft.com/nl59.htm) addressed this problem using
the available simulation techniques. The problems arising out
of the circuit used for the January 2000 newsletter caused us,
here at Intusoft, to explore IsSpice code changes that can solve
the problem in a more efficient manner. It turns out there was
a code fragment left over from an earlier attempt by us to solve
the problem, but was not implemented because we tried to reduce
the time step until a specified voltage accuracy was achieved;
an impossible task for a switching waveform.
Modifying the constraint, on
the other hand, to test for a volt-second error produces the
desired result. The latter method will always find a time step
that is small enough while the earlier method will have a constant
error as the time step is reduced.
We introduced a new option, VSECTOL,
which reduces the time step if the product of the absolute value
of the error in predicted voltage (prediction – solution)
and the time step exceeds the VSECTOL specification. As in most
IsSpice options, its default is zero, which turns the option
off. In testing the new VSECTOL option, we ran some cases setting
RELTO=0.5 and at the same time set VSECTOL to a reasonable value
for the circuit. Figure 5 shows this new time step control option.
Figures 6 and 7 show the results for a simplified power supply
model versus the standard OPTIONS to control the time step. This
introduces a completely new time step control for the simulation,
based on node voltage accuracy. Using snubber.dwg, shown in Figure
5, as a test circuit we ran the usual analysis. All we needed
to do was set VSECTOL=50n, RELTOL=.5 and BYPASS = OFF; no TMAX
was needed in the .tran statement. On the other hand, many parameters
were modified to get spice to run this circuit to completion,
including setting TMAX to 20n. The VSECTOL controlled simulation
ran faster and produced more detail in the switching transitions.
The conventional simulation spent a lot of extra time when the
circuit wasn’t switching and took fewer points in the switching
transition. The Bypass option controls whether or not the device
operating point is calculated for each time step. When Bypass
is ON, these load operations are skipped if errors are low enough.
Since RELTOL is used in the calculations, we can’t use the
BYPASS logic. |