Test Designer Released - New Test designer Redefines Test Software Development

Dateline July 30, 1997 -- Intusoft announced this month...

Intusoft, makers of the popular IsSpice4 simulator, have released a powerful new simulation based test synthesis product called Test Designer. Simply put, Test Designer automates test simulation, fault analysis, fault isolation, and generates detailed test strategy reports. The user can easily pair different circuit configurations with various analyses to create "tests". Tests may detect one or more component failure modes or out-of-tolerance conditions. Measurements such as peak-peak, maximum, rise time, etc. can be assigned to each test. Tolerances are assigned to each measurement in order to grade the performance of each test and determine the pass/fail status. Test Designer runs the entire suite of tests without the need for an operator intervention and creates a test strategy report that summarizes the test results. This powerful capability extends SPICE well beyond its current single simulation-oriented boundaries, and provides a framework for automatic test program software design.Test Designer will be officially introduced at the '97 Design Automation Conference in Anaheim, California.

Test Designer includes a fully integrated schematic entry tool, extensive model libraries, state-of-the-art SPICE3 based analog and mixed signal simulator, a graphical data post processor, and a host of features that handle the test data analysis and reporting. All key data entry, analysis, and reporting features are graphically driven. The user does not have to write any scripts or do any programming in order to define a model, a fault, a measurement, or a test. Over 10,000 part models are provided and most include pre-defined failure modes. For example, all passive and active components use the US Navy CASS "standard" for the default failure modes.

Test Designer features an automated failure analysis capability. This allows you to easily define and select a series of component faults or other out-of-tolerance conditions. The simulator automatically inserts each failure mode without altering the appearance of the schematic, performs the analysis, and removes the fault. The process is repeated without user-intervention, until all faults have been inserted and simulated. Test Designer generates detailed test reports and a fault tree which allows you to develop a test strategy for automated testing.

Unique Features Redefine How The Test Engineer Works
The schematic entry tool integrates all of the relevant design and test information, fault analysis results, and test sequence data. The user does not have to use several different programs. A single schematic database holds multiple circuit configurations, multiple test setups, the fault properties for each part (including both topological variations and parameter value variations), the test definitions, the measurement definitions and tolerances, and all results.

Part faults are defined in a graphical manner using simple dialog entries. The proper netlist for each failed part scenario is generated automatically. The user does not have to "code" any fault behavior. Test measurement scripts are fault analysis and fault grouping data.

Another unique feature is the Quick Edit mode that allows you to make a circuit change and instantly re-simulate in order to see a comparison of current and previous measurement results. A special histogram indicator instantly shows the pass/fail status for each test, and indicates the degree that failed
measurements are out-of-tolerances. You can set asymmetrical pass/fail limits, and tolerances can be set in absolute terms or percent.

Test results are reported for groups of test. An easy to read histogram meter shows the state of each resultant measurement in the group, along with numerical results and test limits. Each measurement can be folded out to show the results for all faults. You can enable or disable test vectors and part fault modes. This allows the engineer to explore different test outcomes without having to repeat the circuit simulations.

Test design is accomplished graphically, by either automatically or manually selecting fault tree nodes from an ordered list which is sorted by test entropy. The results for each fault tree design are shaved with user names and descriptions. A fault tree can be designed all at once or in steps that gradually add more complex tests. The user can look at the results for each fault tree node, examine the underlying tests, and modify the design strategy.

Test results are output to a file in several formats that can be imported to the designer's test programming language. These files contain the logical structure of the tests. The designer only needs to add the test equipment specific coding. The data format is suitable for reports and user documentation.

With Test Designer, test strategies can be improved and debugged by enabling virtual production studies without the need to build a prototype or even wait until the design process has been completed. Test Designer is a vast improvement over current manual test development practices, and dramatically reduces the time consuming process of test software development.

Both coding and debugging of the product have been completed and the Test Designerprogram looks to be a revolutionary product. It will be several months before documentation is completed, but in the mean time, the product is ready to go with its built-in-online help system and tutorials. It requires Windows 95 or Windows NT.


For Further Information Contact:

P.O Box 710
San Pedro, CA
FAX: 310-833-9658