--- Agenda Topics ---

A. Meeting Overview  

B. Circuit Simulation 

C. Failure Analysis, FMEA 

D. Test Synthesis/Sequencing 

E. Questions & Answers 

Session may extend past deadline for additional questions. 

9:30 - 9:45 PM

9:45 - 10:40 PM

10:40 - 11:00 PM

11:00 - 11:30 PM

11:30 - 12:00 PM

The speaker will be available for as long as needed.

Detailed Agenda

  1. Introduction to Intusoft, What Makes Intusoft Different.
  2. ICAP/4Windows overview including description of the schematic entry tool, cross-probing features, waveform analysis tool, and parameter sweeping, plus an in-depth look at the IsSpice4 analog and mixed-signal simulator.
  3. What Does Test Designer Do? Discussion of the FMEA, Failure analysis, and test program set generation features of Test Designer.
  4. A example simulation highlighting key features will be performed.
  5. Discussion of various simulation related topics such as: SPICE Modeling, Modeling of Mechatronic systems (New Mechatronics-SPICE Library), AHDL Modeling, and contents of the ICAP/4 libraries.
  6. Discussions of What Makes Intusoft Different from Competitors.
  7. Description of the schematic database including SPICE attributes, Monte Carlo tolerances, and how part failure modes are entered and characterized.
  8. Description of how to enter a schematic that corresponds to various hardware test setups/fixtures.
  9. Description of the Design Verification and Design Tracking features including automated testing and measurement comparison across multiple simulations.
  10. Description of how a test is setup and test limits are set (Test Synthesis).
  11. Description of how manual and automated failure analysis is performed.
  12. Description of how the fault analysis dictionary is created and viewed.
  13. Description of how a Fault Tree is generated (Test Sequencing) and tests are ordered.
  14. Description of the various reports (ATE independent code, fault dictionary, etc.) produced.

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